1. Field of the Invention
The present invention relates generally to the hermetic sealing of wafer scale silicon wafers having interconnected integrated circuits thereon. More particularly, the present invention involves sealing configurations which reduce the overall size of the hermetically sealed unit for housing the wafer scale integrated wafer.
2. Description of Related Art
Integrated silicon wafers must have their electrically active sections protected in a hermetically sealed enclosure in order for the device to work in a real world environment. The present methods for providing such hermetic sealing involve housing all electronic circuits and hybrids in a hermetic enclosure made of kovar or ceramic. Since most silicon wafers are in the 4-inch (10.2 cm) size range, the hermetic housing structures necessary to surround the electronic assembly have tended to be large and complex. The large size and complexity of such hermetic sealing housings becomes even more of a problem when silicon wafers having diameters in the 5-inch (12.7 cm) to 7-inch (17.8 cm) range are utilized.
In addition to their heavy weight and bulkiness, the separate sealing structures make it difficult to stack the silicon wafers. Accordingly, interwafer signal propagation fidelity and speed are compromised. The size and weight of the hermetically sealed structures also make them undesirable for airborne electronic systems and other uses where the size and weight of the electronic system is minimized.
There presently is a need to provide a new system or configuration for sealing integrated wafers which reduces system size and weight while providing signal integrity gain and increased interwafer signal propagation fidelity and speed.